1. Field of the Invention
The present invention relates to a CMOS arrangement which has at least one NMOS region and at least one PMOS region and which is provided at its surface with substrate contacts, via which it is possible to apply predetermined voltage values to respective substrate sections of the CMOS arrangement.
2. Description of the Related Art
CMOS arrangements of this type have been known for a long time and are extensively used. A practical embodiment of an arrangement of this type is shown in FIG. 2.
FIG. 2 is a diagrammatic cross-sectional view of a conventional CMOS arrangement.
The CMOS arrangement shown has a p.sup.- -type substrate 1, in which an NMOS region 2 and a PMOS region 3 are formed.
An NMOS transistor 21 is formed in the NMOS region 2, the source section 22 of which transistor and the drain section 23 of which transistor are designed as n.sup.+ -regions provided within the p.sup.- -type substrate 1.
In order to realize the PMOS region 3, an n.sup.- -type substrate 30 which is embedded like a trough is provided within the p.sup.- -type substrate 1. A PMOS transistor 31 is formed in this PMOS region 3, the source section 32 of the transistor and the drain section 33 of the transistor are designed as p.sup.+ -type regions provided within the n.sup.- -type substrate 30.
The gate sections as well as the method of operation and the function of the respective transistors are not relevant to the following explanations; therefore, they are neither illustrated in FIG. 2 nor explained in more detail in the description.
The starting point for the further observations is, rather, the pnpn zone sequence in the CMOS arrangement shown in FIG. 2, which is formed by the sequence of (1) source and drain section 32 and 33, respectively, of the PMOS transistor 31, (2) n.sup.- -type substrate 30 of the PMOS transistor 31, (3) p.sup.- -type substrate 1 of the CMOS arrangement and of the NMOS transistor 21 and (4) source and drain section 22 and 23, respectively, of the NMOS transistor 21.
The abovementioned pnpn zone sequence is the zone sequence of a thyristor.
As long as the pn junction between zone (2) and zone (3), i.e. the junction between the n.sup.- -type substrate 30 of the PMOS transistor 31 and the p.sup.- -type substrate 1 of the CMOS arrangement and of the NMOS transistor 21, is in the blocking state, the thyristor is also in the off state and its presence has no effect on the function of the respective transistors.
However, if this junction goes into the conducting state (on account of charge carriers migrating about undesirably in the respective substrates), then the zones (1) and (4), i.e. the source and drain section 32 and 33, respectively, of the PMOS transistor 31 and the source and drain section 22 and 23, respectively, of the NMOS transistor 21, are electrically connected to one another, which leads to incorrect functioning or even to destruction of the respective transistors.
In order to avoid undesirable thyristor effects of this type in CMOS arrangements, i.e. in order to increase the so-called latch-up resistance, the surface of the CMOS arrangement is provided with substrate contacts.
These substrate contacts are realized as p+-type sections 24 that are connected to ground in the NMOS region 2, and as n.sup.+ -type sections 34 connected to a positive voltage in the PMOS region 3. In this way, the charge carriers in question, which render the pn junction conductive, are prevented from freely migrating about in the respective substrates, thereby precluding unintentional triggering of the thyristor.
In order reliably to ensure this effect, however, it is necessary to observe specific maximum distances between neighbouring substrate contacts and between the substrate contacts and the source and drain sections of the respective transistors. A typical maximum value for the distance between neighbouring substrate contacts is approximately 50 .mu.m, and a typical maximum value for the distance between the substrate contacts and the source and drain sections of the respective transistors is approximately 25 .mu.m.
In order to reliably comply with these conditions, the known CMOS arrangements are, as a rule, covered by a uniform grid pattern of substrate contacts. A structure of this type is illustrated in FIG. 3.
FIG. 3 illustrates the arrangement of the substrate contacts on the surface of a conventional CMOS arrangement.
The substrate contacts, which are each marked by a .cndot.(dot), are distributed uniformly over the entire CMOS arrangement, the distance between neighbouring substrate contacts being essentially constantly approximately 50 .mu.m.
It is obvious that the provision of substrate contacts of this type leads to a not inconsiderable enlargement of the CMOS arrangement, or imposes limits on any further miniaturization of the same.